View PE42821_9057444.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

document no. doc-13714-3 www.psemi.com page 1 of 12 ?2012-2013 peregrine semiconductor corp. all rights reserved. figure 2. package type 32-lead 5x5 mm qfn product description the PE42821 is a harp? technology-enhanced high power reflective spdt rf switch designed for use in mobile radio, relay replacement and other high performance wireless applications. this switch is a pin-compatible faster switching version of the pe42820. it maintains high linearity and power handling from 100 mhz through 2.7 ghz. PE42821 also features low insertion loss and is offered in a 32-lead 5x5 mm qfn package. in addition, no external blocking capacitors are required if 0v dc is present on the rf ports. the PE42821 is manufactured on peregrine?s ultracmos ? process, a patented variation of silicon-on- insulator (soi) technology on a sapphire substrate. peregrine?s harp? technology enhancements deliver high linearity and excellent harmonics performance. it is an innovative feature of the ultracmos ? process, offering the performance of gaas with the economy and integration of conventional cmos. product specification figure 1. functional diagram PE42821 features ?? high power handling ?? 45 dbm @ 850 mhz, 32w ?? 44 dbm @ 2 ghz, 25w ?? high linearity ?? 82 dbm iip3 @ 850 mhz ?? 76 dbm iip3 @ 2.7 ghz ?? low insertion loss ?? 0.35 db @ 850 mhz ?? 0.60 db @ 2 ghz ?? fast switching time of 4 s (bypass mode) ?? wide supply range of 2.3v to 5.5v ?? +1.8v control logic compatible ?? esd performance ?? 1.5kv hbm on all pins ?? external negative supply option doc-52312 ultracmos ? spdt rf switch 100 - 2700 mhz
product specification PE42821 page 2 of 12 ?2012-2013 peregrine semiconductor corp. all rights reserved. document no. doc-13714-3 ultracmos ? rfic solutions table 1. electrical specifications @ 25c (z s = z l = 50 ? ) unless otherwise noted normal mode 1 : v dd = 3.3v, vss ext = 0v or bypass mode 2 : v dd = 3.3v, vss ext = -3.3v parameter path condition min typ max unit insertion loss 3 rfc?rfx 100 mhz ? 1 ghz 0.40 0.55 db 1 ghz ? 2 ghz 0.60 0.80 db 2 ghz ? 2.7 ghz 0.80 1.05 db isolation rfx?rfx 100 mhz ? 1 ghz 33 35 db 1 ghz ? 2 ghz 26 28 db 2 ghz ? 2.7 ghz 22 24 db unbiased isolation rfc?rfx v dd , v1 = 0v, +27 dbm 6 db return loss 3 rfx 100 mhz ? 1 ghz 20 db 1 ghz ? 2 ghz 13 db 2 ghz ? 2.7 ghz 14 db harmonics rfc?rfx 2fo: +45 dbm pulsed @ 1ghz, 50 ? 3fo: +45 dbm pulsed @ 1ghz, 50 ? -82 -78 dbc -85 -81 dbc input ip3 rfc?rfx 850 mhz 2700 mhz 82 dbm 76 dbm input 0.1 db compression point 4 rfc-rfx 100 mhz ? 2 ghz 2 ghz ? 2.7 ghz 45.5 44.5 dbm dbm switching time in normal mode 1 50% ctrl to 90% or 10% rf 7 11 s settling time 50% ctrl to harmonics within specifications 5 15 25 s switching time in bypass mode 2 50% ctrl to 90% or 10% rf 4 s notes: 1. normal mode: single external positive supply used 2. bypass mode: both external positive supply and external negative supply used 3. performance specified with external matching. refer to evaluation kit section for additional information 4. the input 0.1db compression point is a linearity figure of merit. refer to table 3 for the operating rf input power (50 ? ) 5. see harmonics specs above
product specification PE42821 page 3 of 12 document no. doc-13714-3 www.psemi.com ?2012-2013 peregrine semiconductor corp. all rights reserved. table 2. pin descriptions table 3. operating ranges figure 3. pin configuration (top view) pin # pin name description 1, 3-11, 14, 15, 17-22, 24-27, 29-32 gnd ground 2 rf1 1 rf port 12 v dd supply voltage (nominal 3.3v) 16 vss ext 2 external vss negative voltage control 23 rf2 1 rf port 28 rfc 1 rf common pad gnd exposed pad: ground for proper operation 13 v1 digital control logic input 1 parameter symbol min typ max unit normal mode 1 supply voltage v dd 2.3 5.5 v supply current i dd 130 200 a bypass mode 2 supply voltage v dd 3.3 5.5 v supply current i dd 50 80 a negative supply voltage vss ext -3.6 -3.2 v negative supply current i ss -40 -16 a digital input high (v1) v ih 1.17 3.6 3 v digital input low (v1) v il -0.3 0.6 v rf input power, cw 100 mhz ? 2 ghz >2 ghz ? 2.7 ghz p max,cw 43 42 dbm dbm rf input power, pulsed 4 100 mhz ? 2 ghz >2 ghz ? 2.7 ghz p max,pulsed 45 44 dbm dbm rf input power, unbiased p max,unb 27 dbm operating temperature range (case) t op -40 +85 c operating junction temperature t j +140 c normal or bypass mode notes: 1. normal mode: connect pin 16 to gnd to enable internal negative voltage generator 2. bypass mode: apply a negative voltage to vss ext (pin 16) to bypass and disable internal negative voltage generator 3. maximum v ih voltage is limited to v dd and cannot exceed 3.6v 4. pulsed, 10% duty cycle of 4620 s period, 50 ? 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 gnd rf1 gnd gnd gnd gnd gnd gnd gnd rf2 gnd gnd gnd gnd gnd gnd exposed ground pad pin 1 dot marking notes: 1. rf pins 2, 23 and 28 must be at 0v dc. the rf pins do not require dc blocking capacitors for proper operat ion if the 0v dc requirement is met 2. use vss ext (pin 16, vss ext = -v dd ) to bypass and disable internal negative voltage generator. connect vss ext (pin 16, vss ext = gnd) to enable internal negative voltage generator
product specification PE42821 page 4 of 12 ?2012-2013 peregrine semiconductor corp. all rights reserved. document no. doc-13714-3 ultracmos ? rfic solutions electrostatic discharge (esd) precautions when handling this ultracmos ? device, observe the same precautions that you would use with other esd-sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the rating specified. latch-up avoidance unlike conventional cmos devices, ultracmos ? devices are immune to latch-up. table 5. control logic truth table path ctrl rfc ? rf1 h rfc ? rf2 l moisture sensitivity level the moisture sensitivity level rating for the 32- lead 5x5 mm qfn package is msl3. table 4. absolute maximum ratings exceeding absolute maximum ratings may cause permanent damage. operation should be restricted to the limits in the operating ranges table. operation between operating range maximum and absolute maximum for extended periods may reduce reliability. parameter/condition symbol min max unit supply voltage v dd -0.3 5.5 v digital input voltage (v1) v ctrl -0.3 3.6 v maximum input power 100 mhz ? 2 ghz >2 ghz ? 2.7 ghz p max,abs 45.5 44.5 dbm dbm storage temperature range t st -65 +150 c maximum case temperature t case +85 c peak maximum junction temperature (10 seconds max) t j +200 c esd voltage hbm 1 , all pins v esd,hbm 1500 v esd voltage mm 2 , all pins v esd,mm 200 v esd voltage cdm 3 , all pins v esd,cdm 250 v notes: 1. human body model (mil-std 883 method 3015) 2. machine model (jedec jesd22-a115) 3. charged device model (jedec jesd22-c101) switching frequency the PE42821 has a maximum 25 khz switching rate in normal mode (pin 16 = gnd). a faster switching rate is available in bypass mode (pin 16 = vss ext ). the rate at which the PE42821 can be switched is then limited to the switching time as specified in table 1 . switching frequency describes the time duration between switching events. switching time is the time duration between the point the control signal reaches 50% of the final value and the point the output signal reaches within 10% or 90% of its target value. spurious performance the typical low-frequency spurious performance of the PE42821 in normal mode is -137 dbm (pin 16 = gnd). if spur-free performance is desired, the internal negative voltage generator can be disabled by applying a negative voltage to vss ext (pin 16). optional external vss control (vss ext ) for applications that require a faster switching rate or spur-free performance, this part can be operated in bypass mode. bypass mode requires an external negative voltage in addition to an external v dd supply voltage. as specified in table 3 , the external negative voltage (vss ext ) when applied to pin 16 will disable and bypass the internal negative voltage generator. hot switching capability the typical hot switching capability of the PE42821 is +30 dbm. hot switching occurs when rf power is applied while switching between rf ports.
product specification PE42821 page 5 of 12 document no. doc-13714-3 www.psemi.com ?2012-2013 peregrine semiconductor corp. all rights reserved. typical performance data @ 25c, v dd = 3.3v, vss ext = 0v unless otherwise noted figure 4. insertion loss vs. temp (rfc?rfx) figure 5. insertion loss vs. v dd (rfc?rfx) figure 6. rfc port return loss vs. temp (rf1 active) figure 7. rfc port return loss vs. v dd (rf1 active)
product specification PE42821 page 6 of 12 ?2012-2013 peregrine semiconductor corp. all rights reserved. document no. doc-13714-3 ultracmos ? rfic solutions typical performance data @ 25c, v dd = 3.3v, vss ext = 0v unless otherwise noted figure 8. active port return loss vs. temp (rf1 active) figure 9. active port return loss vs. v dd (rf1 active) figure 10. isolation vs. temp (rfc?rfx, rfx active) figure 11. isolation vs. v dd (rfc?rfx, rfx active)
product specification PE42821 page 7 of 12 document no. doc-13714-3 www.psemi.com ?2012-2013 peregrine semiconductor corp. all rights reserved. typical performance data @ 25c, v dd = 3.3v, vss ext = 0v unless otherwise noted figure 12. isolation vs. temp (rfx?rfx, rfx active) figure 13. isolation vs. v dd (rfx?rfx, rfx active)
product specification PE42821 page 8 of 12 ?2012-2013 peregrine semiconductor corp. all rights reserved. document no. doc-13714-3 ultracmos ? rfic solutions thermal data though the insertion loss for this part is very low, when handling high power rf signals, the junction temperature rises significantly. vswr conditions that present short circuit loads to the part can cause significantly more power dissipation than with proper matching. special consideration needs to be made in the design of the pcb to properly dissipate the heat away from the part and maintain the 85c maximum case temperature. it is recommended to use best design practices for high power qfn packages: multi-layer pcbs with thermal vias in a thermal pad soldered to the slug of the package. special care also needs to be made to alleviate solder voiding under the part. table 6. theta jc parameter min typ max unit theta jc (+85c) 20 ? c/w
product specification PE42821 page 9 of 12 document no. doc-13714-3 www.psemi.com ?2012-2013 peregrine semiconductor corp. all rights reserved. figure 14. evaluation board layout evaluation kit the PE42821 evaluation kit board was designed to ease customer evaluation of the PE42821 rf switch. the evaluation board in figure 14 was designed to test the part. dc power is supplied through j10, with vdd on pin 9, and gnd on the entire lower row of even numbered pins. to evaluate a switch path, add or remove jumpers on v1 (pin 3) using table 5 . the ant port is connected through a 50 ? transmission line via the top sma connector, j1. rf1 and rf2 paths are also connected through 50 ? transmission lines via sma connectors as j2 and j3. a 50 ? through transmission line is available via sma connectors j5 and j6. this transmission line can be used to estimate the loss of the pcb over the environmental conditions being evaluated. an open-ended 50 ? transmission line is also provided at j4 for calibration if needed. narrow trace widths are used near each part to improve impedance matching. the shunt c1 on rfc port is to provide for high frequency impedance matching. prt-10605
product specification PE42821 page 10 of 12 ?2012-2013 peregrine semiconductor corp. all rights reserved. document no. doc-13714-3 ultracmos ? rfic solutions figure 15. evaluation board schematic doc-13627
product specification PE42821 page 11 of 12 document no. doc-13714-3 www.psemi.com ?2012-2013 peregrine semiconductor corp. all rights reserved. top view bottom view side view recommended land pattern a 0.10 c (2x) c 0.10 c 0.05 c seating plane b 0.10 c (2x) 0.10 c a b 0.05 c all features pin #1 corner 5.00 5.00 3.300.05 3.300.05 3.50 3.50 0.50 0.240.05 (x32) 0.3750.05 (x32) 0.203 ref. 0.05 0.90 max 0.575 (x32) 0.290 (x32) 3.35 5.20 3.35 5.20 0.50 (x28) detail a 1 8 9 16 17 24 25 32 doc-01872 figure 16. package drawing 32-lead 5x5 mm qfn figure 17. top marking specification 42821 yyww zzzzzz 17-0085 = pin 1 indicator yyww = date code, last two digits of the year and work week zzzzzz = six digits of the lot number
product specification PE42821 page 12 of 12 ?2012-2013 peregrine semiconductor corp. all rights reserved. document no. doc-13714-3 ultracmos ? rfic solutions figure 18. tape and reel specs ao = 5.25 0.1 mm bo = 5.25 0.1 mm ko = 1.10 0.1 mm notes: 1. 10 sprocket hole pitch cumulative tolerance 0.2 2. camber in compliance with eia 481 3. pocket position relative to sprocket hole measured as true position of pocket, not pocket hole device orientation in tape top of device pin 1 table 7. ordering information order code description package shipping method PE42821mlba-z PE42821 spdt rf switch green 32-lead 5x5 mm qfn 3000 units/t&r ek42821-02 PE42821 evaluation kit evaluation kit 1/box PE42821mlba-x PE42821 spdt rf switch green 32-lead 5x5 mm qfn 500 units/t&r advance information : the product is in a formative or design stage. the datasheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification: the datasheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification: the datasheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify custom ers of the intended changes by issuing a cnf (customer notification form). the information in this datasheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, ultracmos and utsi are registered trademarks and harp, multiswitch and dune are trademarks of peregrine semiconductor corp. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com . sales contact and information for sales and contact information please visit www.psemi.com .

▲Up To Search▲

Price & Availability of PE42821

	To Download PE42821 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .